180 nm process

The 180 nm process refers to the level of MOSFET (CMOS) semiconductor process technology that was commercialized around the 1998–2000 timeframe by leading semiconductor companies, starting with TSMC^[1] and Fujitsu,^[2] then followed by Sony, Toshiba,^[3] Intel, AMD, Texas Instruments and IBM.

The origin of the 180 nm value is historical, as it reflects a trend of 70% scaling every 2–3 years. The naming is formally determined by the International Technology Roadmap for Semiconductors (ITRS).

Some of the first CPUs manufactured with this process include Intel Coppermine family of Pentium III processors. This was the first technology using a gate length shorter than that of light used for lithography (which has a minimum of 193 nm).

Some more recent microprocessors and microcontrollers (e.g. PIC) are using this technology because it is typically low cost and does not require upgrading of existing equipment.

History[]

In 1988, an IBM research team led by Iranian engineer Bijan Davari fabricated a 180 nm dual-gate MOSFET using a CMOS process.^[4] In 1993, an IBM team led by Hussein I. Hanafi demonstrated a 150 nm CMOS transistor.^[5]

The 180 nm CMOS process was later commercialized by Taiwan Semiconductor Manufacturing Company (TSMC) in 1998,^[1] and then Fujitsu in 1999.^[2]

Processors using 180 nm manufacturing technology[]

Intel Coppermine E – October 1999
Sony PlayStation 2 console's Emotion Engine and Graphics Synthesizer – March 2000^[3]
ATI Radeon R100 and RV100 Radeon 7000 – 2000
AMD Athlon Thunderbird – June 2000
Intel Celeron (Willamette) – May 2002
Motorola PowerPC 7445 and 7455 (Apollo 6) – January 2002

References[]

↑ ^1.0 ^1.1 "0.18-micron Technology". TSMC. Retrieved 30 June 2019.
↑ ^2.0 ^2.1 65nm CMOS Process Technology
↑ ^3.0 ^3.1 "EMOTION ENGINE® AND GRAPHICS SYNTHESIZER USED IN THE CORE OF PLAYSTATION® BECOME ONE CHIP" (PDF). Sony. April 21, 2003. Retrieved 26 June 2019.
↑ Davari, Bijan; et al. (1988). "A high-performance 0.25 micrometer CMOS technology". International Electron Devices Meeting.
↑ Conférence européenne sur la recherche dans les dispositifs à état solide, ed. (1993). ESSDERC'93: proceedings of the 23rd European solid state device research conference, Grenoble, France, 13-16 September 1993. Gif-sur-Yvette: Ed. Frontières. ISBN 978-2-86332-135-5.

Preceded by 250 nm	CMOS manufacturing processes	Succeeded by 130 nm

[tsmc-1] 1.0 ^1.1 "0.18-micron Technology". TSMC. Retrieved 30 June 2019.

[fujitsu-2] 2.0 ^2.1 65nm CMOS Process Technology

[sony2003-3] 3.0 ^3.1 "EMOTION ENGINE® AND GRAPHICS SYNTHESIZER USED IN THE CORE OF PLAYSTATION® BECOME ONE CHIP" (PDF). Sony. April 21, 2003. Retrieved 26 June 2019.

[Davari1988-4] Davari, Bijan; et al. (1988). "A high-performance 0.25 micrometer CMOS technology". International Electron Devices Meeting.

[5] Conférence européenne sur la recherche dans les dispositifs à état solide, ed. (1993). ESSDERC'93: proceedings of the 23rd European solid state device research conference, Grenoble, France, 13-16 September 1993. Gif-sur-Yvette: Ed. Frontières. ISBN 978-2-86332-135-5.

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Semiconductor device fabrication
MOSFET scaling (process nodes)
020 μm – 1968 010 μm – 1971 006 μm – 1974 003 μm – 1977 1.5 μm – 1981 001 μm – 1984 800 nm – 1987 600 nm – 1990 350 nm – 1993 250 nm – 1996 180 nm – 1999 130 nm – 2001 090 nm – 2003 065 nm – 2005 045 nm – 2007 032 nm – 2009 028 nm – 2010 022 nm – 2012 014 nm – 2014 010 nm – 2016 007 nm – 2018 005 nm – 2020 003 nm – 2022
Future 002 nm ~ 2024
Half-nodes Density CMOS Industry Moore's law MOS integrated circuit MOS transistor Multi-gate MOSFET Transistor count Semiconductor Semiconductor device Nanoelectronics
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