| Semiconductor device fabrication |
|---|
|
MOSFET scaling (process nodes) |
|
Future
|
|
The 1 μm process (1 micrometer process) is a level of MOSFET semiconductor process technology that was commercialized around the 1984–1986 timeframe,[1][2] by companies like Nippon Telegraph and Telephone (NTT), NEC, Intel and IBM. It was the first process where CMOS was common (as opposed to NMOS).
The 1 μm process refers to the minimum size that could be reliably produced. The smallest transistors and other circuit elements on a chip made with this process were around 1 micrometer wide.
Technology demonstrations[]
The earliest MOSFET with a 1 μm NMOS channel length was fabricated by a research team led by Robert H. Dennard, Hwa-Nien Yu and F.H. Gaensslen at the IBM T.J. Watson Research Center in 1974.[3]
In 1983, IBM's first CMOS transistor used a 1 μm process developed by Hussein I. Hanafi, G.J. Hu, Yuan Taur, Robert H. Dennard and Chung-Yu Ting.[4][5]
Products featuring 1.0 μm manufacturing process[]
- Nippon Telegraph and Telephone (NTT) in Japan commercially introduced the 1 μm process for its DRAM memory chips, including its 64k in 1979 and 256k in 1980. They were NMOS chips.[6]
- NEC's 1 Mbit DRAM memory chip was manufactured with the 1 μm process in 1984.[7]
- Intel 80386 CPU launched in 1985 was manufactured using this process.[1]
- Intel uses this process on the CHMOS III-E technology by 1989.[8]
- Intel uses this process on the CHMOS IV technology in 1990.[9]
References[]
- ↑ 1.0 1.1 Mueller, S (2006-07-21). "Microprocessors from 1971 to the Present". informIT. Archived from the original on 2015-04-19. Retrieved 2012-05-11.
- ↑ Myslewski, R (2011-11-15). "Happy 40th birthday, Intel 4004!". TheRegister. Archived from the original on 2015-04-19. Retrieved 2015-04-19.
- ↑ Dennard, Robert H.; Yu, Hwa-Nien; Gaensslen, F. H.; Rideout, V. L.; Bassous, E.; LeBlanc, A. R. (October 1974). "Design of ion-implanted MOSFET's with very small physical dimensions" (PDF). IEEE Journal of Solid-State Circuits. 9 (5): 256–268. Bibcode:1974IJSSC...9..256D. doi:10.1109/JSSC.1974.1050511. S2CID 283984.
- ↑ Hussein, Hanafi (2018). "Industry Experience". Tumblr. Retrieved 2024-08-27.
- ↑ Hu, G. J.; Taur, Yuan; Dennard, Robert H.; Terman, L. M.; Ting, Chung-Yu (December 1983). "A self-aligned 1-μm CMOS technology for VLSI". 1983 International Electron Devices Meeting. pp. 739–741. doi:10.1109/IEDM.1983.190615. S2CID 20070619.
- ↑ Gealow, Jeffrey Carl (10 August 1990). "Impact of Processing Technology on DRAM Sense Amplifier Design" (PDF). Massachusetts Institute of Technology. pp. 149–166. Retrieved 25 June 2019 – via CORE.
- ↑ "Memory". STOL (Semiconductor Technology Online). Archived from the original on 2007-10-11. Retrieved 25 June 2019.
- ↑ Intel Corporation, "New Product Focus: Components: Two-and Four-Megabit EPROMs are High-Density Performers", Microcomputer Solutions, September/October 1989, page 14
- ↑ Intel Corporation, "New Product Focus: Components: New ASSP Suits Mobile Applications", Microcomputer Solutions, September/October 1990, page 11
External links[]
| Preceded by 1.5 μm process |
MOSFET semiconductor device fabrication process | Succeeded by 800 nm process |