5 nm process

Semiconductor device fabrication
MOSFET scaling (process nodes)
020 μm – 1968 010 μm – 1971 006 μm – 1974 003 μm – 1977  1.5 μm – 1981 001 μm – 1984 800 nm – 1987 600 nm – 1990 350 nm – 1993 250 nm – 1996 180 nm – 1999 130 nm – 2001 090 nm – 2003 065 nm – 2005 045 nm – 2007 032 nm – 2009 028 nm – 2010 022 nm – 2012 014 nm – 2014 010 nm – 2016 007 nm – 2018 005 nm – 2020 003 nm – 2022
Future 002 nm ~ 2024
Half-nodes Density CMOS Industry Moore's law MOS integrated circuit MOS transistor Multi-gate MOSFET Transistor count Semiconductor Semiconductor device Nanoelectronics

In semiconductor manufacturing, the International Roadmap for Devices and Systems defines the 5 nm process as the MOSFET technology node following the 7 nm node. In 2020, Samsung and TSMC entered volume production of 5 nm chips, manufactured for companies including Apple, Marvell, Huawei and Qualcomm.

The term "5 nanometer" has no relation to any actual physical feature (such as gate length, metal pitch or gate pitch) of the transistors. It is a commercial or marketing term used by the chip fabrication industry to refer to a new, improved generation of silicon semiconductor chips in terms of increased transistor density (i.e. a higher degree of miniaturization), increased speed and reduced power consumption.

History

Background

In 1984, Nippon Telegraph and Telephone (NTT) researchers Toshio Kobayashi, Seiji Horiguchi and K. Kiuchi demonstrated a silicon-gate NMOS transistor with 100 nm channel length and 5 nm oxide thickness.

In 1995, an IBN research team consisting of Hussein I. Hanafi, Farhan Rana, Sandip Tiwari, Wei Chen and Kevin Chan demonstrated nanocrystal memory using MOS transistors with 5 nm to 10 nm nanocrystals. In 1996, Hanafi's team demonstrated nanocrystal memory using MOS transistors with 2 nm to 5 nm nanocrystals. Nanocrystals, also known as quantum dots, are now commonly used in flash memory.

Quantum tunnelling effects through the gate oxide layer on MOS transistors with 7 nm and 5 nm channel lengths became increasingly difficult to manage using existing semiconductor processes.

Single-transistor devices below 7 nm were first demonstrated by researchers in the early 2000s. In 2002, an IBM research team including Omer Dokumaci, Bruce Doris, Meikei Ieong and Anda Mocuta fabricated a 6-nanometre silicon-on-insulator (SOI) MOSFET.

In 2003, a Japanese research team at NEC, led by Hitoshi Wakabayashi and Shigeharu Yamagami, fabricated the first MOSFET with 5 nm channel length.

In 2015, IMEC and Cadence had fabricated 5 nm test chips. The fabricated test chips are not fully functional devices but rather are to evaluate patterning of interconnect layers. In 2015, Intel described a lateral nanowire (or gate-all-around) FET concept for the 5 nm node.

In 2017, IBM revealed that it had created 5 nm silicon chips, using silicon nanosheets in a gate-all-around configuration (GAAFET), a break from the usual FinFET design. The GAAFET transistors used had 3 nanosheets stacked on top of each other, covered in their entirety by the same gate, just like FinFETs usually have several physical fins side by side that are electrically a single unit and are covered in their entirety by the same gate. IBM's chip measured 50 mm² and had 600 million transistors per mm², for a total of 50 billion transistors.

Commercialization

In April 2019, Samsung Electronics announced they had been offering their 5 nm process (5LPE) tools to their customers since 2018 Q4. In April 2019, TSMC announced that their 5 nm process (CLN5FF, N5) had begun risk production, and that full chip design specifications were now available to potential customers. The N5 process can use EUVL on up to 14 layers, compared to only 5 or 4 layers in N6 and N7++. For the expected 28 nm minimum metal pitch, SALELE is the proposed best patterning method.

For their 5 nm process, Samsung started process defect mitigation by automated check and fix, due to occurrence of stochastic (random) defects in the metal and via layers.

In October 2019, TSMC started sampling 5 nm A14 processors for Apple.

In December 2019, TSMC announced an average yield of approximately 80%, with a peak yield per wafer of over 90% for their 5 nm test chips with a die size of 17.92 mm². In mid 2020 TSMC claimed its (N5) 5 nm process offered 1.8x the density of its 7 nm N7 process, with 15% speed improvement or 30% lower power consumption; an improved sub-version (N5P or N4) was claimed to improve on N5 with +5% speed or -10% power.

On October 13, 2020, Apple announced a new iPhone 12 lineup using the A14, together with the Huawei Mate 40 lineup using the HiSilicon Kirin 9000, which were the first devices to be commercialized on TSMC's 5 nm node. Later, on November 10, 2020, Apple also revealed three new Mac models using the Apple M1, another 5 nm chip. According to Semianalysis, the A14 processor has a transistor density of 134 million transistors per mm².

5 nm process nodes

	Samsung	TSMC	IRDS roadmap 2017		Intel
Process name (nm for TSMC & Samsung)	5LPE	N5	7 nm	5 nm	4
Transistor density (MTr/mm2)	127	173	?	?	~200
SRAM bit-cell size (μm2)	0.026	0.017–0.019	0.027	0.020	Un­known
Transistor gate pitch (nm)	57	48	48	42	Un­known
Interconnect pitch (nm)	36	28	28	24	Un­known
Risk production year	2018	2019	2019	2021	2023

Transistor gate pitch is also referred to as CPP (contacted poly pitch) and interconnect pitch is also referred to as MMP (minimum metal pitch).

Beyond 5 nm

Main article: 3 nm process

3 nm (3-nanometer) is the usual term for the next node after 5 nm. since 2021, TSMC plans to commercialize the 3 nm node for 2022, while Samsung and Intel have plans for 2023.

3.5 nm has also been given as a name for the first node beyond 5 nm.

External links

• 5 nm lithography process

Preceded by 7 nm (FinFET)

MOSFET semiconductor device fabrication process

Succeeded by 3 nm