**Fanout** is a measure of the ability of a logic gate, implemented electronically, to drive further logic gates. In most designs, logic gates are connected together to form more complex circuits. The technology used to implement logic gates in general allows gates to be wired directly together with no additional interfacing circuitry required. A perfect logic gate would have infinite input impedance and zero output impedance, allowing a gate to drive any number of further gates.

However, since real-world fabrication technologies exhibit less than perfect characteristics, in reality a limit will be reached where a gate cannot drive any more current into subsequent gates - attempting to do so causes the voltage to fall below the level defined for the logic level on that wire, causing errors.

The fanout is simply the number of gates that can be connected before this occurs.

CMOS logic has a very high fanout - at least 50 to 100, whereas the older TTL logic gates were limited to perhaps 2 to 10, depending on the type of gate. Fanout is also dependent on speed, particularly for the CMOS types, because the input impedance of a gate is largely capacitative and therefore reduces with increasing frequency. This effect is less marked for TTL systems, one reason why they maintained a speed advantage over CMOS for many years.

A related term is "fan-in", which is the measure of the number of gates that can be connected to a single input before errors occur. For CMOS, this can generally be disregarded, but may be a factor for TTL designs.

$ Fanout = \lfloor\frac{I_{out}}{I_{in}}\rfloor $

($ \lfloor\;\rfloor $ is the floor function).

{{enWP|Fan out]]