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Nanoelectronics

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Part of a series of articles on
Nanoelectronics
Solid-state nanoelectronics
Single-molecule electronics
  • Molecular scale electronics
  • Molecular logic gate
  • Molecular wires
Related approaches
  • Nanoionics
  • Nanophotonics
  • Nanomechanics
Part of a series of articles on
Nanotechnology
  • History
  • Organizations
  • Popular culture
  • Outline
Impact and applications
  • Nanomedicine
  • Nanotoxicology
  • Green nanotechnology
  • Hazards
  • Regulation
Nanomaterials
  • Fullerenes
  • Carbon nanotubes
  • Nanoparticles
Molecular self-assembly
  • Self-assembled monolayer
  • Supramolecular assembly
  • DNA nanotechnology
Nanoelectronics
Nanometrology
  • Atomic force microscopy
  • Scanning tunneling microscope
  • Electron microscope
  • Super resolution microscopy
  • Nanotribology
Molecular nanotechnology
  • Molecular assembler
  • Nanorobotics
  • Mechanosynthesis
  • Molecular engineering

Nanoelectronics refers to the use of nanotechnology in electronic components. The term covers a diverse set of devices and materials, with the common characteristic that they are so small that inter-atomic interactions and quantum mechanical properties need to be studied extensively. Some of these candidates include: hybrid molecular/semiconductor electronics, one-dimensional nanotubes/nanowires (e.g. silicon nanowires or carbon nanotubes) or advanced molecular electronics.

Nanoelectronics has origins in the scaling and miniaturization of metal-oxide-semiconductor field-effect transistor (MOSFET) devices, also known as MOS transistors.[1] Nanoelectronic devices have critical dimensions with a size range between 1 nm and 100 nm.[2] Recent silicon MOS transistor technology generations are already within this regime, including 22 nanometer CMOS (complementary MOS) nodes and succeeding 14 nm, 10 nm and 7 nm FinFET (fin field-effect transistor) generations. Nanoelectronics are sometimes considered as disruptive technology because present candidates are significantly different from traditional transistors.

History[]

See also: History of nanotechnology, Multi-gate MOSFET, Semiconductor device fabrication, and Transistor count
Atalla1963
Dawon Kahng
Mohamed Atalla (above) and Dawon Kahng (below) demonstrated MOS transistors with 100 nm gate oxide thickness in 1960, and then a nanolayer-base M–S junction transistor using thin films with 10 nm thickness in 1962.
Semiconductor
device
fabrication
MOSFET scaling
(process nodes)
Future
  • 002 nm ~ 2024

In 1959, Egyptian engineer Mohamed Atalla and Korean engineer Dawon Kahng at Bell Labs invented the first metal-oxide-semiconductor field-effect transistor (MOSFET), also known as MOS transistor.[1] In 1960, they fabricated and demonstrated PMOS and NMOS transistors with a gate length of 10 µm and gate oxide thickness of 100 nm.[3][4] In 1962, Atalla and Kahng fabricated a nanolayer-base metal–semiconductor junction transistor that used gold (Au) thin films with a thickness of 10 nm.[5] This allowed it to operate at a much higher frequency than bipolar transistors of that era.[6]

In 1984, Nippon Telegraph and Telephone (NTT) researchers Toshio Kobayashi, Seiji Horiguchi and K. Kiuchi demonstrated a silicon-gate NMOS transistor with 100 nm channel length and 5 nm oxide thickness.[7] In 1985, NTT researchers Toshio Kobayashi, Seiji Horiguchi, M. Miyake and M. Oda demonstrated NMOS with 150 nm channel length and 2.5 nm oxide thickness.[8] The same year, a Stephen Y. Chou demonstrated NMOS with 75 nm channel length.[9]

In 1985, Egyptian engineer Hisham Z. Massoud introduced the Massoud model.[10] It is the most suitable thermal oxidation model for ultra-thin oxide films,[11] and has since become the most widely used thermal oxidation model in nanoelectronics and nanotechnology.[12]

In 1986, Iranian engineer Ghavam G. Shahidi at MIT fabricated a silicon NMOS transistor with 60 nanometer channel length and 7.5 nm oxide thickness.[13][14] The device was fabricated using X-ray lithography.[15] In 1987, Iranian engineer Bijan Davari led an IBM research team that demonstrated a MOSFET with 10 nm gate oxide thickness using tungsten-gate technology.[16]

In 1995, an IBN research team consisting of Hussein I. Hanafi, Farhan Rana, Sandip Tiwari, Wei Chen and Kevin Chan demonstrated nanocrystal memory using MOS transistors with 5 nm to 10 nm nanocrystals.[17][18][19] In 1996, they demonstrated nanocrystal memory using MOS transistors with 2 nm to 5 nm nanocrystals.[20] Nanocrystals, also known as quantum dots, are now commonly used in flash memory.[21]

Multi-gate MOSFETs enabled scaling below 20 nm gate length, starting with the FinFET (fin field-effect transistor), a three-dimensional, non-planar, double-gate MOSFET.[22] The FinFET originates from the DELTA transistor developed by Hitachi Central Research Laboratory's Digh Hisamoto, Toru Kaga, Yoshifumi Kawamoto and Eiji Takeda in 1989.[23][24][25] Using silicon on insulator (SOI) technology, the DELTA transistor had 200 nm gate length.[26] In 1990, a 100 nm CMOS process was demonstrated by Iranian engineers Ghavam G. Shahidi and Bijan Davari.[27]

In 1995, an IBM team led by Hussein I. Hanafi demonstrated nanocrystal memory using MOS transistors with 5 nm to 10 nm nanocrystals.[28][29][30] They then demonstrated nanocrystal memory using MOS transistors with 2 nm to 5 nm nanocrystals.[31] Nanocrystals, also known as quantum dots, are now commonly used in flash memory.[32]

Indonesian engineer Effendi Leobandung, while working at the University of Minnesota, published a paper with Stephen Y. Chou at the 54th Device Research Conference in 1996 outlining the benefit of cutting a wide CMOS transistor into many channels with narrow width to improve device scaling and increase device current by increasing the effective device width.[33] This structure is what a modern FinFET looks like.[34] The device had a 35 nm channel width and 70 nm channel length.[33]

In 1997, DARPA awarded a contract to a research group at UC Berkeley to develop a deep sub-micron DELTA transistor.[25] The group consisted of Hisamoto along with TSMC's Chenming Hu and other international researchers including Tsu-Jae King Liu, Shibly Ahmed, Cyrus Tabery, Jeffrey Bokor, Hideki Takeuchi, K. Asano, Jakub Kedziersk, Xuejue Huang, Leland Chang and Nick Lindert. The team successfully fabricated FinFET devices down to a 17 nm process in 1998, and then 15 nm in 2001. In 2002, a team including Yu, Chang, Ahmed, Tabery, Hu, Liu and Bokor fabricated a 10 nm FinFET device.[22]

In 1999, a CMOS (complementary MOS) transistor developed at the Laboratory for Electronics and Information Technology in Grenoble, France, tested the limits of the principles of the MOSFET transistor with a diameter of 18 nm (approximately 70 atoms placed side by side). It enabled the theoretical integration of seven billion junctions on a €1 coin. However, the CMOS transistor was not a simple research experiment to study how CMOS technology functions, but rather a demonstration of how this technology functions now that we ourselves are getting ever closer to working on a molecular scale. According to Jean-Baptiste Waldner in 2007, it would be impossible to master the coordinated assembly of a large number of these transistors on a circuit and it would also be impossible to create this on an industrial level.[35]

In 2006, a team of Korean researchers from the Korea Advanced Institute of Science and Technology (KAIST) and the National Nano Fab Center developed a 3 nm MOSFET, the world's smallest nanoelectronic device. It was based on gate-all-around (GAA) FinFET technology.[36][37]

Commercial production of nanoelectronic semiconductor devices began in the 2010s. In 2013, SK Hynix began commercial mass-production of a 16 nm process,[38] TSMC began production of a 16 nm FinFET process,[39] and Samsung Electronics began production of a 10 nm class process.[40] TSMC began production of a 7 nm process in 2017,[41] and Samsung began production of a 5 nm process in 2018.[42] In 2017, TSMC announced plans for the commercial production of a 3 nm process by 2022.[43] In 2019, Samsung announced plans for a 3 nm GAAFET (gate-all-around FET) process by 2021.[44]

Timeline[]

See also: List of semiconductor scale examples and Transistor density
Date Channel length Oxide thickness[45] MOSFET Researcher(s) Organization Ref
June 1960 20,000 nm 100 nm PMOS Mohamed M. Atalla, Dawon Kahng Bell Telephone Laboratories [46][47]
NMOS
10,000 nm 100 nm PMOS Mohamed M. Atalla, Dawon Kahng Bell Telephone Laboratories [48]
NMOS
October 1966 100,000 100 TFT T.P. Brody, H.E. Kunig Westinghouse Electric [49][50]
1968 20,000 nm 100 nm CMOS ? RCA Laboratories [51]
1970 10,000 nm 100 nm CMOS ? RCA Laboratories [51]
October 1974 1,000 nm 35 nm NMOS Hwa-Nien Yu, Robert H. Dennard, Fritz H. Gaensslen IBM T.J. Watson Research Center [52]
500 nm
September 1975 1,500 nm 20 nm NMOS Ryoichi Hori, Hiroo Masuda, Osamu Minato Hitachi [53][54]
April 1979 1,000 nm 25 nm NMOS William R. Hunter, L. M. Ephrath, Alice Cramer IBM T.J. Watson Research Center [55]
February 1983 1,200 nm 25 nm CMOS R.J.C. Chwang, M. Choi, D. Creek, S. Stern, P.H. Pelley Intel [56][57]
900 nm 15 nm CMOS Tsuneo Mano, J. Yamada, Junichi Inoue, S. Nakajima Nippon Telegraph and Telephone (NTT) [56][58]
December 1983 1,000 nm 22.5 nm CMOS G.J. Hu, Yuan Taur, Robert H. Dennard, Chung-Yu Ting IBM T.J. Watson Research Center [59]
December 1984 100 nm 5 nm NMOS Toshio Kobayashi, Seiji Horiguchi, K. Kiuchi Nippon Telegraph and Telephone [60]
December 1985 150 nm 2.5 nm NMOS Toshio Kobayashi, Seiji Horiguchi, M. Miyake, M. Oda Nippon Telegraph and Telephone [61]
75 nm ? NMOS Stephen Y. Chou, Henry I. Smith, Dimitri A. Antoniadis MIT [62]
January 1986 60 nm ? NMOS Stephen Y. Chou, Henry I. Smith, Dimitri A. Antoniadis MIT [63]
November 1986 90 8.3 ? Han-Sheng Lee, L.C. Puzio General Motors [64]
December 1986 60 ? ? Ghavam G. Shahidi, Dimitri A. Antoniadis, Henry I. Smith MIT [65][66]
February 1987 800 nm 17 nm CMOS T. Sumi, Tsuneo Taniguchi, Mikio Kishimoto, Hiroshige Hirano Matsushita [56][67]
700 nm 12 nm CMOS Tsuneo Mano, J. Yamada, Junichi Inoue, S. Nakajima Nippon Telegraph and Telephone [56][68]
May 1987 ? 10 ? Bijan Davari, Chung-Yu Ting, Kie Y. Ahn, S. Basavaiah IBM T.J. Watson Research Center [69]
June 1987 200 nm 3.5 nm PMOS Toshio Kobayashi, M. Miyake, K. Deguchi Nippon Telegraph and Telephone [70]
September 1987 500 nm 12.5 nm CMOS Hussein I. Hanafi, Robert H. Dennard, Yuan Taur, Nadim F. Haddad IBM T.J. Watson Research Center [71]
February 1988 400 nm 10 nm CMOS M. Inoue, H. Kotani, T. Yamada, Hiroyuki Yamauchi Matsushita [56][72]
December 1990 100 nm ? CMOS Ghavam G. Shahidi, Bijan Davari, Yuan Taur, James D. Warnock IBM T.J. Watson Research Center [73]
December 1993 40 nm ? NMOS Mizuki Ono, Masanobu Saito, Takashi Yoshitomi Toshiba [74]
September 1996 16 nm ? PMOS Hisao Kawaura, Toshitsugu Sakamoto, Toshio Baba NEC [75]
June 1997 30 ? EJ-MOSFET Hisao Kawaura, Toshitsugu Sakamoto, Toshio Baba NEC [76]
June 1998 50 nm 1.3 nm NMOS Khaled Z. Ahmed, Effiong E. Ibok, Miryeong Song Advanced Micro Devices (AMD) [77][78]
December 1998 17 nm ? FinFET Digh Hisamoto, Chenming Hu, Tsu-Jae King Liu, Jeffrey Bokor University of California (Berkeley) [79][80]
1998 32 ? ? ? NEC [81]
1999 8
April 2000 8 ? EJ-MOSFET Hisao Kawaura, Toshitsugu Sakamoto, Toshio Baba NEC [82]
2001 15 nm ? FinFET Chenming Hu, Yang‐Kyu Choi, Nick Lindert, Tsu-Jae King Liu University of California (Berkeley) [79][83]
December 2002 6 nm ? PMOS Bruce Doris, Omer Dokumaci, Meikei Ieong IBM [84][85][86]
December 2002 10 nm ? FinFET Shibly Ahmed, Scott Bell, Cyrus Tabery, Jeffrey Bokor University of California (Berkeley) [79][87]
December 2003 3 nm ? PMOS Hitoshi Wakabayashi, Shigeharu Yamagami NEC [88][85]
NMOS
December 2003 5 nm ? CMOS Hitoshi Wakabayashi, Shigeharu Yamagami, Nobuyuki Ikezawa NEC [89][90]
June 2006 3 nm ? GAAFET Hyunjin Lee, Yang-kyu Choi, Lee-Eun Yu, Seong-Wan Ryu KAIST [91][92]

Fundamental concepts[]

In 1965, Gordon Moore observed that silicon transistors were undergoing a continual process of scaling downward, an observation which was later codified as Moore's law. Since his observation, transistor minimum feature sizes have decreased from 10 micrometers to the 10 nm range as of 2019. Note that the technology node doesn't directly represent the minimum feature size. The field of nanoelectronics aims to enable the continued realization of this law by using new methods and materials to build electronic devices with feature sizes on the nanoscale.

Mechanical issues[]

The volume of an object decreases as the third power of its linear dimensions, but the surface area only decreases as its second power. This somewhat subtle and unavoidable principle has huge ramifications. For example, the power of a drill (or any other machine) is proportional to the volume, while the friction of the drill's bearings and gears is proportional to their surface area. For a normal-sized drill, the power of the device is enough to handily overcome any friction. However, scaling its length down by a factor of 1000, for example, decreases its power by 10003 (a factor of a billion) while reducing the friction by only 10002 (a factor of only a million). Proportionally it has 1000 times less power per unit friction than the original drill. If the original friction-to-power ratio was, say, 1%, that implies the smaller drill will have 10 times as much friction as power; the drill is useless.

For this reason, while super-miniature electronic integrated circuits are fully functional, the same technology cannot be used to make working mechanical devices beyond the scales where frictional forces start to exceed the available power. So even though you may see microphotographs of delicately etched silicon gears, such devices are currently little more than curiosities with limited real world applications, for example, in moving mirrors and shutters.[93] Surface tension increases in much the same way, thus magnifying the tendency for very small objects to stick together. This could possibly make any kind of "micro factory" impractical: even if robotic arms and hands could be scaled down, anything they pick up will tend to be impossible to put down. The above being said, molecular evolution has resulted in working cilia, flagella, muscle fibers and rotary motors in aqueous environments, all on the nanoscale. These machines exploit the increased frictional forces found at the micro or nanoscale. Unlike a paddle or a propeller which depends on normal frictional forces (the frictional forces perpendicular to the surface) to achieve propulsion, cilia develop motion from the exaggerated drag or laminar forces (frictional forces parallel to the surface) present at micro and nano dimensions. To build meaningful "machines" at the nanoscale, the relevant forces need to be considered. We are faced with the development and design of intrinsically pertinent machines rather than the simple reproductions of macroscopic ones.

All scaling issues therefore need to be assessed thoroughly when evaluating nanotechnology for practical applications.

Approaches[]

Nanofabrication[]

Main articles: Nanocircuitry and nanolithography

For example, electron transistors, which involve transistor operation based on a single electron. Nanoelectromechanical systems also fall under this category. Nanofabrication can be used to construct ultradense parallel arrays of nanowires, as an alternative to synthesizing nanowires individually.[94][95] Of particular prominence in this field, Silicon nanowires are being increasingly studied towards diverse applications in nanoelectronics, energy conversion and storage. Such SiNWs can be fabricated by thermal oxidation in large quantities to yield nanowires with controllable thickness.

Nanomaterials electronics[]

Besides being small and allowing more transistors to be packed into a single chip, the uniform and symmetrical structure of nanowires and/or nanotubes allows a higher electron mobility (faster electron movement in the material), a higher dielectric constant (faster frequency), and a symmetrical electron/hole characteristic.[96]

Also, nanoparticles can be used as quantum dots.

Molecular electronics[]

Main article: Molecular scale electronics

Single molecule devices are another possibility. These schemes would make heavy use of molecular self-assembly, designing the device components to construct a larger structure or even a complete system on their own. This can be very useful for reconfigurable computing, and may even completely replace present FPGA technology.

Molecular electronics[97] is a new technology which is still in its infancy, but also brings hope for truly atomic scale electronic systems in the future. One of the more promising applications of molecular electronics was proposed by the IBM researcher Ari Aviram and the theoretical chemist Mark Ratner in their 1974 and 1988 papers Molecules for Memory, Logic and Amplification, (see Unimolecular rectifier).[98][99]

This is one of many possible ways in which a molecular level diode / transistor might be synthesized by organic chemistry. A model system was proposed with a spiro carbon structure giving a molecular diode about half a nanometre across which could be connected by polythiophene molecular wires. Theoretical calculations showed the design to be sound in principle and there is still hope that such a system can be made to work.

Other approaches[]

Nanoionics studies the transport of ions rather than electrons in nanoscale systems.

Nanophotonics studies the behavior of light on the nanoscale, and has the goal of developing devices that take advantage of this behavior.

Nanoelectronic devices[]

Current high-technology production processes are based on traditional top down strategies, where nanotechnology has already been introduced silently. The critical length scale of integrated circuits is already at the nanoscale (50 nm and below) regarding the gate length of transistors in CPUs or DRAM devices.

Computers[]

Threshold formation nowatermark

Simulation result for formation of inversion channel (electron density) and attainment of threshold voltage (IV) in a nanowire MOSFET. Note that the threshold voltage for this device lies around 0.45V.

Nanoelectronics holds the promise of making computer processors more powerful than are possible with conventional semiconductor fabrication techniques. A number of approaches are currently being researched, including new forms of nanolithography, as well as the use of nanomaterials such as nanowires or small molecules in place of traditional CMOS components. Field effect transistors have been made using both semiconducting carbon nanotubes[100] and with heterostructured semiconductor nanowires (SiNWs).[101]

Memory storage[]

Electronic memory designs in the past have largely relied on the formation of transistors. However, research into crossbar switch based electronics have offered an alternative using reconfigurable interconnections between vertical and horizontal wiring arrays to create ultra high density memories. Two leaders in this area are Nantero which has developed a carbon nanotube based crossbar memory called Nano-RAM and Hewlett-Packard which has proposed the use of memristor material as a future replacement of Flash memory.

An example of such novel devices is based on spintronics. The dependence of the resistance of a material (due to the spin of the electrons) on an external field is called magnetoresistance. This effect can be significantly amplified (GMR - Giant Magneto-Resistance) for nanosized objects, for example when two ferromagnetic layers are separated by a nonmagnetic layer, which is several nanometers thick (e.g. Co-Cu-Co). The GMR effect has led to a strong increase in the data storage density of hard disks and made the gigabyte range possible. The so-called tunneling magnetoresistance (TMR) is very similar to GMR and based on the spin dependent tunneling of electrons through adjacent ferromagnetic layers. Both GMR and TMR effects can be used to create a non-volatile main memory for computers, such as the so-called magnetic random access memory or MRAM.

Commercial production of nanoelectronic memory began in the 2010s. In 2013, SK Hynix began mass-production of 16 nm NAND flash memory,[38] and Samsung Electronics began production of 10 nm multi-level cell (MLC) NAND flash memory.[40] In 2017, TSMC began production of SRAM memory using a 7 nm process.[41]

Novel optoelectronic devices[]

In the modern communication technology traditional analog electrical devices are increasingly replaced by optical or optoelectronic devices due to their enormous bandwidth and capacity, respectively. Two promising examples are photonic crystals and quantum dots. Photonic crystals are materials with a periodic variation in the refractive index with a lattice constant that is half the wavelength of the light used. They offer a selectable band gap for the propagation of a certain wavelength, thus they resemble a semiconductor, but for light or photons instead of electrons. Quantum dots are nanoscaled objects, which can be used, among many other things, for the construction of lasers. The advantage of a quantum dot laser over the traditional semiconductor laser is that their emitted wavelength depends on the diameter of the dot. Quantum dot lasers are cheaper and offer a higher beam quality than conventional laser diodes.

Displays[]

The production of displays with low energy consumption might be accomplished using carbon nanotubes (CNT) and/or Silicon nanowires. Such nanostructures are electrically conductive and due to their small diameter of several nanometers, they can be used as field emitters with extremely high efficiency for field emission displays (FED). The principle of operation resembles that of the cathode ray tube, but on a much smaller length scale.

Quantum computers[]

Main article: Quantum computer

Entirely new approaches for computing exploit the laws of quantum mechanics for novel quantum computers, which enable the use of fast quantum algorithms. The Quantum computer has quantum bit memory space termed "Qubit" for several computations at the same time. This facility may improve the performance of the older systems.

Radios[]

Nanoradios have been developed structured around carbon nanotubes.[102]

Energy production[]

Research is ongoing to use nanowires and other nanostructured materials with the hope to create cheaper and more efficient solar cells than are possible with conventional planar silicon solar cells.[103] It is believed that the invention of more efficient solar energy would have a great effect on satisfying global energy needs.

There is also research into energy production for devices that would operate in vivo, called bio-nano generators. A bio-nano generator is a nanoscale electrochemical device, like a fuel cell or galvanic cell, but drawing power from blood glucose in a living body, much the same as how the body generates energy from food. To achieve the effect, an enzyme is used that is capable of stripping glucose of its electrons, freeing them for use in electrical devices. The average person's body could, theoretically, generate 100 watts of electricity (about 2000 food calories per day) using a bio-nano generator.[104] However, this estimate is only true if all food was converted to electricity, and the human body needs some energy consistently, so possible power generated is likely much lower. The electricity generated by such a device could power devices embedded in the body (such as pacemakers), or sugar-fed nanorobots. Much of the research done on bio-nano generators is still experimental, with Panasonic's Nanotechnology Research Laboratory among those at the forefront.

Medical diagnostics[]

There is great interest in constructing nanoelectronic devices[105][106][107] that could detect the concentrations of biomolecules in real time for use as medical diagnostics,[108] thus falling into the category of nanomedicine.[109] A parallel line of research seeks to create nanoelectronic devices which could interact with single cells for use in basic biological research.[110] These devices are called nanosensors. Such miniaturization on nanoelectronics towards in vivo proteomic sensing should enable new approaches for health monitoring, surveillance, and defense technology.[111][112][113]

References[]

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  23. ↑ Colinge, J.P. (2008). FinFETs and Other Multi-Gate Transistors. Springer Science & Business Media. p. 11. ISBN 9780387717517.
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