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Semiconductor device fabrication is the process used to manufacture semiconductor devices, typically the metal–oxide–semiconductor (MOS) devices used in the MOS integrated circuit (MOS IC) chips that are present in everyday electrical and electronic devices. It is a multiple-step sequence of photolithographic and chemical processing steps (such as surface passivation, thermal oxidation, planar diffusion and junction isolation) during which electronic circuits are gradually created on a wafer made of pure semiconducting material. Silicon is almost always used, but various compound semiconductors are used for specialized applications.
The entire manufacturing process, from start to packaged chips ready for shipment, takes six to eight weeks and is performed in highly specialized facilities referred to as foundries or fabs.[1] In more advanced semiconductor devices, such as modern 14/10/7 nm nodes, fabrication can take up to 15 weeks (about 4 months) with 11–13 weeks (3 to 4 months) being the industry average.[2] Production in advanced fabrication facilities is completely automated, and carried out in a hermetically sealed, nitrogen environment to improve yield (the proportion of microchips in a wafer that function correctly) with FOUPs and automated material handling systems taking care of the transport of wafers from machine to machine. All machinery as well as FOUPs contain an internal nitrogen atmosphere. The air inside the machinery and the FOUPs is usually kept cleaner than the surrounding air in the cleanroom. This internal atmosphere is known as a mini environment.[3] Fab's need for large amounts of liquid nitrogen arises from the need to maintain the nitrogen atmosphere inside production machinery and FOUPs, which are constantly purged with nitrogen.[4]
By industry standard, each generation of the semiconductor manufacturing process, also known as technology node, is designated by the process’ minimum feature size. Technology nodes, also known as "process technologies" or simply "nodes", are typically indicated by the size in nanometers (or historically micrometers) of the process' transistor gate length.
History[]
- See also: List of semiconductor scale examples, Moore's law, MOS integrated circuit, Semiconductor industry, Silicon Age, and Transistor density
20th century[]
In the early years of the semiconductor industry, up until the late 1950s, germanium was the dominant semiconductor material for transistors and other semiconductor devices, rather than silicon. Germanium was initially considered the more effective semiconductor material, as it was able to demonstrate better performance due to higher carrier mobility.[5][6] The relative lack of performance in early silicon semiconductors was due to electrical conductivity being limited by unstable quantum surface states,[7] where electrons are trapped at the surface, due to dangling bonds that occur because unsaturated bonds are present at the surface.[8] This prevented electricity from reliably penetrating the surface to reach the semiconducting silicon layer. Mohamed M. Atalla eventually overcame this problem with his silicon surface passivation process developed at Bell Labs in 1957, which was a key step towards the proliferation of silicon integrated circuits.[9][10][11]
The metal–oxide–semiconductor field-effect transistor (MOSFET), also known as MOS transistor, was invented by Egyptian engineer Mohamed M. Atalla and Korean engineer Dawon Kahng at Bell Labs in 1959.[12] They originally demonstrated two types of MOSFET technology in 1960, PMOS (p-type MOS) and NMOS (n-type MOS).[13] Both types were developed by Atalla and Kahng when they originally invented the MOSFET, fabricating both PMOS and NMOS devices at 20 µm[12] and 10 µm scales.[14]
An improved type of MOSFET technology, CMOS, was developed by Chih-Tang Sah and Frank Wanlass at Fairchild Semiconductor in 1963.[15][16] CMOS was commercialised by RCA in the late 1960s.[15] RCA commercially used CMOS for its 4000-series integrated circuits in 1968, starting with a 20 µm process before gradually scaling to a 10 µm process over the next several years.[17]
Semiconductor device manufacturing has since spread from Texas and California in the 1960s to the rest of the world, including Asia, Europe, and the Middle East.
21st century[]
The semiconductor industry is a global business today. The leading semiconductor manufacturers typically have facilities all over the world. Samsung Electronics, the world's largest manufacturer of semiconductors, has facilities in South Korea and the US. Intel, the second largest manufacturer, has facilities in Europe and Asia as well as the US. TSMC, the world's largest pure play foundry, has facilities in Taiwan, China, Singapore, and the US. Qualcomm and Broadcom are among the biggest fabless semiconductor companies, outsourcing their production to companies like TSMC.[18] They also have facilities spread in different countries.
Since 2009, "node" has become a commercial name for marketing purposes that indicates new generations of process technologies, without any relation to gate length, metal pitch or gate pitch.[19][20][21] For example, GlobalFoundries' 7 nm process is similar to Intel's 10 nm process, thus the conventional notion of a process node has become blurred.[22] Additionally, TSMC and Samsung's 10 nm processes are only slightly denser than Intel's 14 nm in transistor density. They are actually much closer to Intel's 14 nm process than they are to Intel's 10 nm process (e.g. Samsung's 10 nm processes' fin pitch is the exact same as that of Intel's 14 nm process: 42 nm).[23][24]
As of 2019, 14 nanometer and 10 nanometer chips are in mass production by Intel, UMC, TSMC, Samsung, Micron, SK Hynix, Toshiba Memory and GlobalFoundries, with 7 nanometer process chips in mass production by TSMC and Samsung, although their 7 nanometer node definition is similar to Intel's 10 nanometer process. The 5 nanometer process began being produced by Samsung in 2018.[25] As of 2019, the node with the highest transistor density is TSMC's 5 nanometer N5 node,[26] with a density of 171.3 million transistors per square millimeter.[27] In 2019, Samsung and TSMC announced plans to produce 3 nanometer nodes. GlobalFoundries has decided to stop the development of new nodes beyond 12 nanometers in order to save resources, as it has determined that setting up a new fab to handle sub-12nm orders would be beyond the company's financial abilities.[28] since 2019[update], Samsung is the industry leader in advanced semiconductor scaling, followed by TSMC and then Intel.[29]
List of steps[]
This is a list of processing techniques that are employed numerous times throughout the construction of a modern electronic device; this list does not necessarily imply a specific order. Equipment for carrying out these processes is made by a handful of companies. All equipment needs to be tested before a semiconductor fabrication plant is started. [30]
- Wafer processing
- Wet cleans
- Cleaning by solvents such as acetone, trichloroethylene and Ultrapure water
- Piranha solution
- RCA clean
- Surface passivation
- Photolithography
- Ion implantation (in which dopants are embedded in the wafer creating regions of increased or decreased conductivity)
- Dry etching
- Reactive-ion etching
- Atomic layer etching (ALE)
- Wet etching
- Plasma ashing
- Thermal treatments
- Rapid thermal anneal
- Furnace anneals
- Thermal oxidation
- Chemical vapor deposition (CVD)
- Atomic layer deposition (ALD)
- Physical vapor deposition (PVD)
- Molecular beam epitaxy (MBE)
- Laser lift-off (for LED production[31])
- Electrochemical deposition (ECD). See Electroplating
- Chemical-mechanical polishing (CMP)
- Wafer testing (where the electrical performance is verified using Automatic Test Equipment, laser trimming may also be carried out at this step)
- Wet cleans
- Die preparation
- Through-silicon via manufacture (For three-dimensional integrated circuits)
- Wafer mounting (wafer is mounted onto a metal frame using Dicing tape)
- Wafer backgrinding and polishing[32] (reduces the thickness of the wafer for thin devices like a smartcard or PCMCIA card or wafer bonding and stacking, this can also occur during wafer dicing, in a process known as Dice Before Grind or DBG[33][34])
- Wafer bonding and stacking (For Three-dimensional integrated circuits and MEMS)
- Redistribution layer manufacture (for WLCSP packages)
- Wafer Bumping (For Flip Chip BGA, and WLCSP packages)
- Die cutting or Wafer dicing
- IC packaging
- Die attachment (The die is attached to the leadframe using conductive paste or die attach film[35][36])
- IC bonding: Wire bonding, Thermosonic bonding, Flip chip or Tape Automated Bonding (TAB)
- IC encapsulation
- Molding (using special Molding compound)
- Baking
- Electroplating (plates the copper leads of the lead frames with tin to make soldering easier)
- Lasermarking
- Trim and form (separates the lead frames from each other, and bends the lead frame's pins so that they can be mounted on a Printed circuit board)
- IC testing
Prevention of contamination and defects[]
When feature widths were far greater than about 10 micrometres, semiconductor purity was not as big of an issue as it is today in device manufacturing. As devices became more integrated, cleanrooms must become even cleaner. Today, fabrication plants are pressurized with filtered air to remove even the smallest particles, which could come to rest on the wafers and contribute to defects. The workers in a semiconductor fabrication facility are required to wear cleanroom suits to protect the devices from human contamination. To prevent oxidation and to increase yield, FOUPs and semiconductor capital equipment may have a pure nitrogen environment with ISO class 1 levels of dust.
Wafers[]
A typical wafer is made out of extremely pure silicon that is grown into mono-crystalline cylindrical ingots (boules) up to 300 mm (slightly less than 12 inches) in diameter using the Czochralski process. These ingots are then sliced into wafers about 0.75 mm thick and polished to obtain a very regular and flat surface.
Processing[]
In semiconductor device fabrication, the various processing steps fall into four general categories: deposition, removal, patterning, and modification of electrical properties.
- Deposition is any process that grows, coats, or otherwise transfers a material onto the wafer. Available technologies include physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE) and more recently, atomic layer deposition (ALD) among others. Deposition can be understood to include oxide layer formation, by thermal oxidation or, more specifically, LOCOS.
- Removal is any process that removes material from the wafer; examples include etch processes (either wet or dry) and chemical-mechanical planarization (CMP).
- Patterning is the shaping or altering of deposited materials, and is generally referred to as lithography. For example, in conventional lithography, the wafer is coated with a chemical called a photoresist; then, a machine called a stepper focuses, aligns, and moves a mask, exposing select portions of the wafer below to short wavelength light; the exposed regions are washed away by a developer solution. After etching or other processing, the remaining photoresist is removed by plasma ashing.
- Modification of electrical properties has historically entailed doping transistor sources and drains (originally by diffusion furnaces and later by ion implantation). These doping processes are followed by furnace annealing or, in advanced devices, by rapid thermal annealing (RTA); annealing serves to activate the implanted dopants. Modification of electrical properties now also extends to the reduction of a material's dielectric constant in low-k insulators via exposure to ultraviolet light in UV processing (UVP). Modification is frequently achieved by oxidation, which can be carried out to create semiconductor-insulator junctions, such as in the local oxidation of silicon (LOCOS) to fabricate metal oxide field effect transistors.
Modern chips have up to eleven metal levels produced in over 300 sequenced processing steps.
Front-end-of-line (FEOL) processing[]
FEOL processing refers to the formation of the transistors directly in the silicon. The raw wafer is engineered by the growth of an ultrapure, virtually defect-free silicon layer through epitaxy. In the most advanced logic devices, prior to the silicon epitaxy step, tricks are performed to improve the performance of the transistors to be built. One method involves introducing a straining step wherein a silicon variant such as silicon-germanium (SiGe) is deposited. Once the epitaxial silicon is deposited, the crystal lattice becomes stretched somewhat, resulting in improved electronic mobility. Another method, called silicon on insulator technology involves the insertion of an insulating layer between the raw silicon wafer and the thin layer of subsequent silicon epitaxy. This method results in the creation of transistors with reduced parasitic effects.
Gate oxide and implants[]
Front-end surface engineering is followed by growth of the gate dielectric (traditionally silicon dioxide), patterning of the gate, patterning of the source and drain regions, and subsequent implantation or diffusion of dopants to obtain the desired complementary electrical properties. In dynamic random-access memory (DRAM) devices, storage capacitors are also fabricated at this time, typically stacked above the access transistor (the now defunct DRAM manufacturer Qimonda implemented these capacitors with trenches etched deep into the silicon surface).
Back-end-of-line (BEOL) processing[]
Metal layers[]
Once the various semiconductor devices have been created, they must be interconnected to form the desired electrical circuits. This occurs in a series of wafer processing steps collectively referred to as BEOL (not to be confused with back end of chip fabrication, which refers to the packaging and testing stages). BEOL processing involves creating metal interconnecting wires that are isolated by dielectric layers. The insulating material has traditionally been a form of SiO2 or a silicate glass, but recently new low dielectric constant materials are being used (such as silicon oxycarbide), typically providing dielectric constants around 2.7 (compared to 3.82 for SiO2), although materials with constants as low as 2.2 are being offered to chipmakers.
Interconnect[]
Historically, the metal wires have been composed of aluminum. In this approach to wiring (often called subtractive aluminum), blanket films of aluminum are deposited first, patterned, and then etched, leaving isolated wires. Dielectric material is then deposited over the exposed wires. The various metal layers are interconnected by etching holes (called "vias") in the insulating material and then depositing tungsten in them with a CVD technique; this approach is still used in the fabrication of many memory chips such as dynamic random-access memory (DRAM), because the number of interconnect levels is small (currently no more than four).
More recently, as the number of interconnect levels for logic has substantially increased due to the large number of transistors that are now interconnected in a modern microprocessor, the timing delay in the wiring has become so significant as to prompt a change in wiring material (from aluminum to copper interconnect layer) and a change in dielectric material (from silicon dioxides to newer low-K insulators). This performance enhancement also comes at a reduced cost via damascene processing, which eliminates processing steps. As the number of interconnect levels increases, planarization of the previous layers is required to ensure a flat surface prior to subsequent lithography. Without it, the levels would become increasingly crooked, extending outside the depth of focus of available lithography, and thus interfering with the ability to pattern. CMP (chemical-mechanical planarization) is the primary processing method to achieve such planarization, although dry etch back is still sometimes employed when the number of interconnect levels is no more than three.
Wafer test[]
The highly serialized nature of wafer processing has increased the demand for metrology in between the various processing steps. For example, thin film metrology based on ellipsometry or reflectometry is used to tightly control the thickness of gate oxide, as well as the thickness, refractive index and extinction coefficient of photoresist and other coatings. Wafer test metrology equipment is used to verify that the wafers haven't been damaged by previous processing steps up until testing; if too many dies on one wafer have failed, the entire wafer is scrapped to avoid the costs of further processing. Virtual metrology has been used to predict wafer properties based on statistical methods without performing the physical measurement itself.[1]
Device test[]
Once the front-end process has been completed, the semiconductor devices are subjected to a variety of electrical tests to determine if they function properly. The proportion of devices on the wafer found to perform properly is referred to as the yield. Manufacturers are typically secretive about their yields, but it can be as low as 30%, meaning that only 30% of the chips on the wafer work as intended. Process variation is one among many reasons for low yield.[37]
The number of defects (yield) is proportional to device size. As an example, In December 2019, TSMC announced an average yield of ~80%, with a peak yield per wafer of >90% for their 5nm test chips with a die size of 17.92 mm2. The yield went down to 32.0% with an increase in die size to 100 mm2. [38]
The fab tests the chips on the wafer with an electronic tester that presses tiny probes against the chip. The machine marks each bad chip with a drop of dye. Currently, electronic dye marking is possible if wafer test data is logged into a central computer database and chips are "binned" (i.e. sorted into virtual bins) according to the predetermined test limits. The resulting binning data can be graphed, or logged, on a wafer map to trace manufacturing defects and mark bad chips. This map can also be used during wafer assembly and packaging.
Chips are also tested again after packaging, as the bond wires may be missing, or analog performance may be altered by the package. This is referred to as the "final test".
Usually, the fab charges for testing time, with prices in the order of cents per second. Testing times vary from a few milliseconds to a couple of seconds, and the test software is optimized for reduced testing time. Multiple chip (multi-site) testing is also possible, because many testers have the resources to perform most or all of the tests in parallel.
Chips are often designed with "testability features" such as scan chains or a "built-in self-test" to speed testing, and reduce testing costs. In certain designs that use specialized analog fab processes, wafers are also laser-trimmed during testing, in order to achieve tightly-distributed resistance values as specified by the design.
Good designs try to test and statistically manage corners (extremes of silicon behavior caused by a high operating temperature combined with the extremes of fab processing steps). Most designs cope with at least 64 corners.
Die preparation[]
Once tested, a wafer is typically reduced in thickness in a process also known as "backlap",[39] "backfinish" or "wafer thinning"[40] before the wafer is scored and then broken into individual dice, a process known as wafer dicing. Only the good, unmarked chips are packaged.
Packaging[]
Plastic or ceramic packaging involves mounting the die, connecting the die pads to the pins on the package, and sealing the die. Tiny bondwires are used to connect the pads to the pins. Specialized machines perform the task. Traditionally, these wires have been composed of gold, leading to a lead frame (pronounced "leed frame") of solder-plated copper; lead is poisonous, so lead-free "lead frames" are now mandated by RoHS.
Chip scale package (CSP) is another packaging technology. A plastic dual in-line package, like most packages, is many times larger than the actual die hidden inside, whereas CSP chips are nearly the size of the die; a CSP can be constructed for each die before the wafer is diced.
The packaged chips are retested to ensure that they were not damaged during packaging and that the die-to-pin interconnect operation was performed correctly. A laser then etches the chip's name and numbers on the package.
Hazardous materials[]
- See also: Health hazards in semiconductor manufacturing occupations
Many toxic materials are used in the fabrication process.[41] These include:
- poisonous elemental dopants, such as arsenic, antimony, and phosphorus.
- poisonous compounds, such as arsine, phosphine, and silane.
- highly reactive liquids, such as hydrogen peroxide, fuming nitric acid, sulfuric acid, and hydrofluoric acid.
It is vital that workers should not be directly exposed to these dangerous substances. The high degree of automation common in the IC fabrication industry helps to reduce the risks of exposure. Most fabrication facilities employ exhaust management systems, such as wet scrubbers, combustors, heated absorber cartridges, etc., to control the risk to workers and to the environment.
Timeline of MOSFET demonstrations[]
- See also: MOSFET
PMOS and NMOS[]
Date | Channel length | Oxide thickness[42] | MOSFET logic | Researcher(s) | Organization | Ref |
---|---|---|---|---|---|---|
June 1960 | 20,000 nm | 100 nm | PMOS | Mohamed M. Atalla, Dawon Kahng | Bell Telephone Laboratories | [43][44] |
NMOS | ||||||
10,000 nm | 100 nm | PMOS | Mohamed M. Atalla, Dawon Kahng | Bell Telephone Laboratories | [45] | |
NMOS | ||||||
May 1965 | 8,000 nm | 150 nm | NMOS | Chih-Tang Sah, Otto Leistiko, A.S. Grove | Fairchild Semiconductor | [46] |
5,000 nm | 170 nm | PMOS | ||||
December 1972 | 1,000 nm | ? | PMOS | Hwa-Nien Yu, Robert H. Dennard, Fritz H. Gaensslen | IBM T.J. Watson Research Center | [47][48][49] |
1973 | 7,500 nm | ? | NMOS | Sohichi Suzuki | NEC | [50][51] |
6,000 nm | ? | PMOS | ? | Toshiba | [52][53] | |
October 1974 | 1,000 nm | 35 nm | NMOS | Hwa-Nien Yu, Robert H. Dennard, Fritz H. Gaensslen | IBM T.J. Watson Research Center | [54] |
500 nm | ||||||
September 1975 | 1,500 nm | 20 nm | NMOS | Ryoichi Hori, Hiroo Masuda, Osamu Minato | Hitachi | [48][55] |
March 1976 | 3,000 nm | ? | NMOS | ? | Intel | [56] |
April 1979 | 1,000 nm | 25 nm | NMOS | William R. Hunter, L. M. Ephrath, Alice Cramer | IBM T.J. Watson Research Center | [57] |
December 1984 | 100 nm | 5 nm | NMOS | Toshio Kobayashi, Seiji Horiguchi, K. Kiuchi | Nippon Telegraph and Telephone | [58] |
December 1985 | 150 nm | 2.5 nm | NMOS | Toshio Kobayashi, Seiji Horiguchi, M. Miyake, M. Oda | Nippon Telegraph and Telephone | [59] |
75 nm | ? | NMOS | Stephen Y. Chou, Henry I. Smith, Dimitri A. Antoniadis | MIT | [60] | |
January 1986 | 60 nm | ? | NMOS | Stephen Y. Chou, Henry I. Smith, Dimitri A. Antoniadis | MIT | [61] |
December 1986 | 60 nm | ? | ? | Ghavam G. Shahidi, Dimitri A. Antoniadis, Henry I. Smith | MIT | [62][63][61] |
May 1987 | 400 nm | 10 nm | NMOS | Bijan Davari, Chung-Yu Ting, Kie Y. Ahn, S. Basavaiah | IBM T.J. Watson Research Center | [64] |
June 1987 | 200 nm | 3.5 nm | PMOS | Toshio Kobayashi, M. Miyake, K. Deguchi | Nippon Telegraph and Telephone | [65] |
December 1993 | 40 nm | ? | NMOS | Mizuki Ono, Masanobu Saito, Takashi Yoshitomi | Toshiba | [66] |
September 1996 | 16 nm | ? | PMOS | Hisao Kawaura, Toshitsugu Sakamoto, Toshio Baba | NEC | [67] |
June 1998 | 50 nm | 1.3 nm | NMOS | Khaled Z. Ahmed, Effiong E. Ibok, Miryeong Song | Advanced Micro Devices (AMD) | [68][69] |
December 2002 | 6 nm | ? | PMOS | Bruce Doris, Omer Dokumaci, Meikei Ieong | IBM | [70][71][72] |
December 2003 | 3 nm | ? | PMOS | Hitoshi Wakabayashi, Shigeharu Yamagami | NEC | [73][71] |
NMOS |
CMOS (single-gate)[]
Date | Channel length | Oxide thickness[42] | Researcher(s) | Organization | Ref |
---|---|---|---|---|---|
February 1963 | ? | ? | Chih-Tang Sah, Frank Wanlass | Fairchild Semiconductor | [15][74] |
1968 | 20,000 nm | 100 nm | ? | RCA Laboratories | [17] |
1970 | 10,000 nm | 100 nm | ? | RCA Laboratories | [17] |
December 1976 | 2,000 nm | ? | A. Aitken, R.G. Poulsen, A.T.P. MacArthur, J.J. White | Mitel Semiconductor | [75] |
February 1978 | 3,000 nm | ? | Toshiaki Masuhara, Osamu Minato, Toshio Sasaki, Yoshio Sakai | Hitachi Central Research Laboratory | [76][77][78] |
February 1983 | 1,200 nm | 25 nm | R.J.C. Chwang, M. Choi, D. Creek, S. Stern, P.H. Pelley | Intel | [79][80] |
900 nm | 15 nm | Tsuneo Mano, J. Yamada, Junichi Inoue, S. Nakajima | Nippon Telegraph and Telephone (NTT) | [79][81] | |
December 1983 | 1,000 nm | 22.5 nm | G.J. Hu, Yuan Taur, Robert H. Dennard, Chung-Yu Ting | IBM T.J. Watson Research Center | [82] |
February 1987 | 800 nm | 17 nm | T. Sumi, Tsuneo Taniguchi, Mikio Kishimoto, Hiroshige Hirano | Matsushita | [79][83] |
700 nm | 12 nm | Tsuneo Mano, J. Yamada, Junichi Inoue, S. Nakajima | Nippon Telegraph and Telephone (NTT) | [79][84] | |
September 1987 | 500 nm | 12.5 nm | Hussein I. Hanafi, Robert H. Dennard, Yuan Taur, Nadim F. Haddad | IBM T.J. Watson Research Center | [85] |
December 1987 | 250 nm | ? | Naoki Kasai, Nobuhiro Endo, Hiroshi Kitajima | NEC | [86] |
February 1988 | 400 nm | 10 nm | M. Inoue, H. Kotani, T. Yamada, Hiroyuki Yamauchi | Matsushita | [79][87] |
December 1990 | 100 nm | ? | Ghavam G. Shahidi, Bijan Davari, Yuan Taur, James D. Warnock | IBM T.J. Watson Research Center | [88] |
1993 | 350 nm | ? | ? | Sony | [89] |
1996 | 150 nm | ? | ? | Mitsubishi Electric | |
1998 | 180 nm | ? | ? | TSMC | [90] |
December 2003 | 5 nm | ? | Hitoshi Wakabayashi, Shigeharu Yamagami, Nobuyuki Ikezawa | NEC | [73][91] |
Multi-gate MOSFET (MuGFET)[]
Date | Channel length | MuGFET type | Researcher(s) | Organization | Ref |
---|---|---|---|---|---|
1987 | 2,000 nm | DGMOS | Toshihiro Sekigawa | Electrotechnical Laboratory (ETL) | [92] |
December 1988 | 250 nm | DGMOS | Bijan Davari, Wen-Hsing Chang, Matthew R. Wordeman, C.S. Oh | IBM T.J. Watson Research Center | [93][94] |
180 nm | |||||
? | GAAFET | Fujio Masuoka, Hiroshi Takato, Kazumasa Sunouchi, N. Okabe | Toshiba | [95][96][97] | |
December 1989 | 200 nm | FinFET | Digh Hisamoto, Toru Kaga, Yoshifumi Kawamoto, Eiji Takeda | Hitachi Central Research Laboratory | [98][99][100] |
December 1998 | 17 nm | FinFET | Digh Hisamoto, Chenming Hu, Tsu-Jae King Liu, Jeffrey Bokor | University of California (Berkeley) | [101][102] |
2001 | 15 nm | FinFET | Chenming Hu, Yang‐Kyu Choi, Nick Lindert, Tsu-Jae King Liu | University of California (Berkeley) | [101][103] |
December 2002 | 10 nm | FinFET | Shibly Ahmed, Scott Bell, Cyrus Tabery, Jeffrey Bokor | University of California (Berkeley) | [101][104] |
June 2006 | 3 nm | GAAFET | Hyunjin Lee, Yang-kyu Choi, Lee-Eun Yu, Seong-Wan Ryu | KAIST | [105][106] |
Other types of MOSFET[]
Date | Channel length (nm) |
Oxide thickness (nm)[42] |
MOSFET type |
Researcher(s) | Organization | Ref |
---|---|---|---|---|---|---|
October 1962 | ? | ? | TFT | Paul K. Weimer | RCA Laboratories | [107][108] |
1965 | ? | ? | GaAs | H. Becke, R. Hall, J. White | RCA Laboratories | [109] |
October 1966 | 100,000 | 100 | TFT | T.P. Brody, H.E. Kunig | Westinghouse Electric | [110][111] |
August 1967 | ? | ? | FGMOS | Dawon Kahng, Simon Min Sze | Bell Telephone Laboratories | [112] |
October 1967 | ? | ? | MNOS | H.A. Richard Wegener, A.J. Lincoln, H.C. Pao | Sperry Corporation | [113] |
July 1968 | ? | ? | BiMOS | Hung-Chang Lin, Ramachandra R. Iyer | Westinghouse Electric | [114][115] |
October 1968 | ? | ? | BiCMOS | Hung-Chang Lin, Ramachandra R. Iyer, C.T. Ho | Westinghouse Electric | [116][115] |
1969 | ? | ? | VMOS | ? | Hitachi | [117][118] |
September 1969 | ? | ? | DMOS | Y. Tarui, Y. Hayashi, Toshihiro Sekigawa | Electrotechnical Laboratory (ETL) | [119][120] |
October 1970 | ? | ? | ISFET | Piet Bergveld | University of Twente | [121][122] |
October 1970 | 1000 | ? | DMOS | Y. Tarui, Y. Hayashi, Toshihiro Sekigawa | Electrotechnical Laboratory (ETL) | [123] |
1977 | ? | ? | VDMOS | John Louis Moll | HP Labs | [117] |
? | ? | LDMOS | ? | Hitachi | [124] | |
July 1979 | ? | ? | IGBT | Bantval Jayant Baliga, Margaret Lazeri | General Electric | [125] |
December 1984 | 2000 | ? | BiCMOS | H. Higuchi, Goro Kitsukawa, Takahide Ikeda, Y. Nishio | Hitachi | [126] |
May 1985 | 300 | ? | ? | K. Deguchi, Kazuhiko Komatsu, M. Miyake, H. Namatsu | Nippon Telegraph and Telephone | [127] |
February 1985 | 1000 | ? | BiCMOS | H. Momose, Hideki Shibata, S. Saitoh, Jun-ichi Miyamoto | Toshiba | [128] |
November 1986 | 90 | 8.3 | ? | Han-Sheng Lee, L.C. Puzio | General Motors | [129] |
September 1987 | ? | 10 | ? | Hussein I. Hanafi, Ting, Chung-Yu, Ahn, Kie Y. | IBM T.J. Watson Research Center | [130] |
December 1987 | 800 | ? | BiCMOS | Robert H. Havemann, R. E. Eklund, Hiep V. Tran | Texas Instruments | [131] |
June 1997 | 30 | ? | EJ-MOSFET | Hisao Kawaura, Toshitsugu Sakamoto, Toshio Baba | NEC | [132] |
1998 | 32 | ? | ? | ? | NEC | [71] |
1999 | 8 | |||||
April 2000 | 8 | ? | EJ-MOSFET | Hisao Kawaura, Toshitsugu Sakamoto, Toshio Baba | NEC | [133] |
Timeline of commercial MOSFET nodes[]
See also[]
- List of semiconductor scale examples
- MOSFET
- Multigate device
- Semiconductor industry
- Foundry model
- Semiconductor equipment sales leaders by year
- International Technology Roadmap for Semiconductors
- Semiconductor consolidation
- Local oxidation of silicon (LOCOS)
- List of integrated circuit manufacturers
- List of semiconductor fabrication plants
- Microfabrication
- Semiconductor Equipment and Materials International (SEMI) — the semiconductor industry trade association
- SEMI font for labels on wafers
- Etch pit density
- Passivation
- Planar process
- Transistor count
References[]
- ↑ 1.0 1.1 Neurotechnology Group, Berlin Institute of Technology, IEEE Xplore Digital Library. “Regression Methods for Virtual Metrology of Layer Thickness in Chemical Vapor Deposition.” January 17, 2014. Retrieved November 9, 2015.
- ↑ "8 Things You Should Know About Water & Semiconductors". ChinaWaterRisk.org. Retrieved 2017-09-10.
- ↑ https://pdfs.semanticscholar.org/5c00/0e7c2022761af486e82bceb6ba541e2bd6de.pdf
- ↑ "FOUP Purge System - Fabmatics: Semiconductor Manufacturing Automation". www.fabmatics.com.
- ↑ Dabrowski, Jarek; Müssig, Hans-Joachim (2000). "6.1. Introduction". Silicon Surfaces and Formation of Interfaces: Basic Science in the Industrial World. World Scientific. pp. 344–346. ISBN 978-981-02-3286-3.
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- ↑ Bergveld, P. (January 1970). "Development of an Ion-Sensitive Solid-State Device for Neurophysiological Measurements". IEEE Transactions on Biomedical Engineering. BME-17 (1): 70–71. doi:10.1109/TBME.1970.4502688. PMID 5441220.
- ↑ Chris Toumazou; Pantelis Georgiou (December 2011). "40 years of ISFET technology: From neuronal sensing to DNA sequencing". Electronics Letters. doi:10.1049/el.2011.3231. Retrieved 13 May 2016.
- ↑ Tarui, Y.; Hayashi, Y.; Sekigawa, Toshihiro (October 1970). "DSA enhancement – Depletion MOS IC". 1970 International Electron Devices Meeting: 110. doi:10.1109/IEDM.1970.188299.
- ↑ Duncan, Ben (1996). High Performance Audio Power Amplifiers. Elsevier. pp. 177–8, 406. ISBN 9780080508047.
- ↑ Baliga, B. Jayant (2015). The IGBT Device: Physics, Design and Applications of the Insulated Gate Bipolar Transistor. William Andrew. pp. xxviii, 5–12. ISBN 9781455731534.
- ↑ Higuchi, H.; Kitsukawa, Goro; Ikeda, Takahide; Nishio, Y.; Sasaki, N.; Ogiue, Katsumi (December 1984). "Performance and structures of scaled-down bipolar devices merged with CMOSFETs". 1984 International Electron Devices Meeting: 694–697. doi:10.1109/IEDM.1984.190818. S2CID 41295752.
- ↑ Deguchi, K.; Komatsu, Kazuhiko; Miyake, M.; Namatsu, H.; Sekimoto, M.; Hirata, K. (1985). "Step-and-Repeat X-ray/Photo Hybrid Lithography for 0.3 μm Mos Devices". 1985 Symposium on VLSI Technology. Digest of Technical Papers: 74–75.
- ↑ Momose, H.; Shibata, Hideki; Saitoh, S.; Miyamoto, Jun-ichi; Kanzaki, K.; Kohyama, Susumu (1985). "1.0-/spl mu/m n-Well CMOS/Bipolar Technology". IEEE Journal of Solid-State Circuits. 20 (1): 137–143. Bibcode:1985IJSSC..20..137M. doi:10.1109/JSSC.1985.1052286. S2CID 37353920.
- ↑ Lee, Han-Sheng; Puzio, L.C. (November 1986). "The electrical properties of subquarter-micrometer gate-length MOSFET's". IEEE Electron Device Letters. 7 (11): 612–614. Bibcode:1986IEDL....7..612H. doi:10.1109/EDL.1986.26492. S2CID 35142126.
- ↑ Davari, Bijan; Ting, Chung-Yu; Ahn, Kie Y.; Basavaiah, S.; Hu, Chao-Kun; Taur, Yuan; Wordeman, Matthew R.; Aboelfotoh, O.; Krusin-Elbaum, L.; Joshi, Rajiv V.; Polcari, Michael R. (1987). "Submicron Tungsten Gate MOSFET with 10 nm Gate Oxide". 1987 Symposium on VLSI Technology. Digest of Technical Papers: 61–62.
- ↑ Havemann, Robert H.; Eklund, R. E.; Tran, Hiep V.; Haken, R. A.; Scott, D. B.; Fung, P. K.; Ham, T. E.; Favreau, D. P.; Virkus, R. L. (December 1987). "An 0.8 #181;m 256K BiCMOS SRAM technology". 1987 International Electron Devices Meeting: 841–843. doi:10.1109/IEDM.1987.191564. S2CID 40375699.
- ↑ Kawaura, Hisao; Sakamoto, Toshitsugu; Baba, Toshio; Ochiai, Yukinori; Fujita, Jun-ichi; Matsui, Shinji; Sone, J. (1997). "Transistor operations in 30-nm-gate-length EJ-MOSFETs". 1997 55th Annual Device Research Conference Digest: 14–15. doi:10.1109/DRC.1997.612456. ISBN 0-7803-3911-8. S2CID 38105606.
- ↑ Kawaura, Hisao; Sakamoto, Toshitsugu; Baba, Toshio (12 June 2000). "Observation of source-to-drain direct tunneling current in 8 nm gate electrically variable shallow junction metal–oxide–semiconductor field-effect transistors". Applied Physics Letters. 76 (25): 3810–3812. Bibcode:2000ApPhL..76.3810K. doi:10.1063/1.126789. ISSN 0003-6951.
Further reading[]
- Kaeslin, Hubert (2008), Digital Integrated Circuit Design, from VLSI Architectures to CMOS Fabrication, Cambridge University Press, section 14.2.
- Wiki related to Chip Technology